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IRF9204PbF
D.U.T
+
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
+
?
-
Circuit Layout Considerations
? Low Stray Inductance
? Ground Plane
? Low Leakage Inductance
Current Transformer
D.U.T. I SD Waveform
V GS =10V *
D.U.T. V DS Waveform
?
?
-
R G
?
?
?
?
- ? +
dv/dt controlled by R G
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
V DD
+
-
Reverse
Recovery
Current
Re-Applied
Voltage
Inductor Curent
Body Diode Forward
Current
di/dt
Diode Recovery
dv/dt
Body Diode Forward Drop
V DD
Ripple  ≤  5%
I SD
* V GS = 5V for Logic Level Devices
Fig 16. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET ? Power MOSFETs
V (BR)DSS
15V
tp
VDS
L
DRIVER
RG
GS
20V
tp
D.U.T
IAS
0.01 Ω
+
-
VDD
A
I AS
Fig 17a. Unclamped Inductive Test Circuit
Fig 17b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
50K Ω
Vds
Vgs
Id
12V
.2 μ F
.3 μ F
- DS
V GS
3mA
D.U.T.
+
V
V gs(th)
I G
I D
Current Sampling Resistors
Qgs1 Qgs2
Qgd
Qgodr
Fig 18a. Gate Charge Test Circuit
Fig 18b. Gate Charge Waveform
V DS
R D
V DS
- V DD
R G
V GS
D.U.T.
+
90%
10V
Pulse Width ≤ 1 μs
Duty Factor ≤ 0.1 %
10%
V GS
t d(on)
t r
t d(off)
t f
6
Fig 19a. Switching Time Test Circuit
Fig 19b. Switching Time Waveforms
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